The present invention relates to a semiconductor design technology and, more particularly, to a circuit for receiving a signal to be input into a semiconductor device. Furthermore, the present invention relates to a circuit for receiving a signal to be input into a semiconductor device using a reference voltage which is produced in the semiconductor device.
Generally, in order to execute a predetermined internal operation in a semiconductor device, the semiconductor device needs various signals, such as clock signals, command signals, and data signals, supplied from an external circuit.
At this time, the external circuit transfers various signals to the semiconductor device via a transmission line which has an unspecified length and is made of an unspecified material because the signals are processed in signal processing units, such as a controller adjacent to the semiconductor device and an electric circuit which is directly controlled by a user.
That is, the signals can be distorted and deformed by various noise until the signals are input into the semiconductor device, regardless of the origination of the signals.
Accordingly, the semiconductor device includes a receiver to receive the various signals from an external circuit so that the signals normally can be used in the internal operation thereof.
FIG. 1 is a circuit diagram illustrating a conventional signal receiving circuit to receive a signal from an external circuit.
Referring to FIG. 1, the conventional signal receiving circuit, which receives signals CLK, CLKb and OUT_SIG supplied from an external circuit, has two methods for receiving the signals, even if they have slightly different configurations.
That is, the conventional signal receiving circuit, which receives signals CLK, CLKb and OUT_SIG supplied from the external circuit, includes a receiving circuit 100 to receive a positive clock signal CLK and a negative click signal CLKb and to output an internal clock signal iCLK and a receiving circuit 120 to receive an external signal OUT_SIG from an external circuit and to output an internal signal IN_SIG based on a potential level of a reference voltage VREF_IN supplied from the external circuit.
First, the receiving circuit 100 receives the positive and negative clock signals CLK and CLKb, which have the same frequency and are out of phase with each other, and includes a differential amplifier 102 to amplify a voltage difference between the positive clock signal CLK through a positive input terminal (+) and the negative clock signal CLKb through a negative input terminal (−), and a signal driving unit 104 to output an internal clock signal iCLK by driving a logic determination level according to an output signal from the differential amplifier 102.
The differential amplifier 102 includes first to third NMOS transistors N11 to N13 and first and second PMOS transistors P11 and P12. The first NMOS transistor N11 controls the amount of a current flowing from a drain-connected driving node DVND to a source-connected common node COMN in response to the positive clock signal CLK applied to this first NMOS transistor's gate. The second NMOS transistor N12 controls the amount of a current flowing from a drain-connected output node OUND to the source-connected common node COMN in response to the negative clock signal CLKb applied to this second NMOS transistor's gate. The first and second PMOS transistors P11 and P12 are coupled to each other in a current mirror type among a power supply voltage terminal VDD, the driving node DVND and the output node OUND in order to control an amount of current in such a manner that the amount of current flowing into the driving node DVND is the same as that flowing into the output node OUND. The third NMOS transistor N13 controls an amount of current flowing between the common node COMN and a ground voltage terminal VSS in response to an enable signal applied to a gate thereof.
The signal driving unit 104 includes a third PMOS transistor P13 and a fourth NMOS transistor N14. The third PMOS transistor P13 controls an amount of current flowing from a source-connected power supply voltage terminal VDD to a drain-connected driving node KND in response to a differential amplified voltage signal DFFER_AMP_VOL from the output node OUND of the differential amplifier 102. The fourth NMOS transistor N14 controls an amount of current flowing from a drain-connected driving node KND to a source-connected ground voltage terminal VSS in response to the differential amplified voltage signal DFFER_AMP_VOL from the output node OUND of the differential amplifier 102.
At this time, since the positive clock signal CLK is out of phase with the negative clock signal CLKb, it is easy to generate the internal clock signal iCLK by determining a voltage level through a receiving process in the receiving circuit 100, which receives the positive clock signal CLK and the negative clock signal CLKb, even if there is an unexpected distortion or deformity caused by a noise while the positive clock signal CLK and the negative clock signal CLKb are input into the receiving circuit 100.
That is, one of noise characteristics is that the simultaneously transferred signals have the same amount of noise. Since the positive clock signal CLK and the negative clock signal CLKb are simultaneously transferred, the positive clock signal CLK and the negative clock signal CLKb have the same distortion and deformity caused by the same noise effect in the receiving signals. Accordingly, although an unexpected noise has an effect on the positive clock signal CLK and the negative clock signal CLKb which are out of phase with each other, it is not possible to make the positive clock signal CLK changed into the negative clock signal CLKb.
Therefore, in the receiving circuit 100 to receive the positive clock signal CLK and the negative clock signal CLKb, it is easy to determine a voltage level of the internal clock signal iCLK using a voltage difference between the positive clock signal CLK and the negative clock signal CLKb and an accuracy of the voltage determination between the positive clock signal CLK and the negative clock signal CLKb is also high.
However, since the positive clock signal CLK and the negative clock signal CLKb are continuously toggled signals and they generally operate in high frequency, the positive clock signal CLK and the negative clock signal CLKb have to be controlled, in such a way that the positive clock signal CLK and the negative clock signal CLKb swing in a range of a CML region, for an effective signal transmission of the positive clock signal CLK and the negative clock signal CLKb.
At this time, the CML region means a common mode level. In the CML region, the maximum potential level VILmax is lower than the power supply voltage VDD and the minimum potential level VIHmin is higher than the ground voltage VSS.
That is, since it is not preferred, in terms of a current consumption, that the signals are continuously toggled in the high frequency, the current consumption of the transmission of the positive clock signal CLK and the negative clock signal CLKb has to be reduced maximally, by controlling the swing widths of the positive clock signal CLK and the negative clock signal CLKb and then making the swing widths of the positive clock signal CLK and the negative clock signal CLKb have relatively small values.
Furthermore, after the completion of the transmission of the positive clock signal CLK and the negative clock signal CLKb, the internal clock signal iCLK corresponding to the positive clock signal CLK and the negative clock signal CLKb has to be used in the semiconductor device without any problem, by controlling the swing widths of the positive clock signal CLK and the negative clock signal CLKb and then making the swing widths of the positive clock signal CLK and the negative clock signal CLKb have relatively large values.
Accordingly, in the receiving circuit 100 to receive the positive clock signal CLK and the negative clock signal CLKb, the internal clock signal iCLK is controlled in such a manner that the internal clock signal iCLK swing in a range of a CMOS region which is correspondent to clock edges of the positive clock signal CLK and the negative clock signal CLKb, by shifting the maximum potential level VILmax and the minimum potential level VIHmin to the power supply voltage VDD and the ground voltage VSS, respectively, through the receiving process of the positive clock signal CLK and the negative clock signal CLKb.
At this time, in the CMOS region, the maximum potential level VILmax is the same as the voltage level of the power supply voltage VDD and the minimum potential level VIHmin is the same as the voltage level of the ground voltage VSS. That is, the CMOS region means a full swing signal between the power supply voltage VDD and the ground voltage VSS.
A receiving circuit 120 receives an external signal OUT_SIG, which does not have a specific frequency, and includes a differential amplifier 122 and a signal driving unit 124. The differential amplifier 122, as a psudo differential amplifier, amplifies a voltage difference between a reference voltage VREDF_IN at a predetermined voltage level through a positive input terminal (+) and the external signal OUT_SIG through a negative input terminal (−). The signal driving unit 124 outputs an internal signal IN_SIG by driving a logic determination level according to an output signal from the differential amplifier 122.
For reference, the differential amplifier 122 included in the receiving circuit 120 to receive the external signal OUT_SIG has the same configuration as the differential amplifier 102 included in the receiving circuit 100 to receive the positive clock signal CLK and the negative clock signal CLKb. However, as mentioned above, the differential amplifier 122 is used as the psudo differential amplifier.
In more detail, in the differential amplifier 102 included in the receiving circuit 100 to receive the positive clock signal CLK and the negative clock signal CLKb, the positive clock signal CLK and the negative clock signal CLKb are out of phase with each other so that they are differential signals. Therefore, the differential amplifier 102 included in the receiving circuit 100 actually executes the differential amplification between the positive clock signal CLK and the negative clock signal CLKb.
However, since the external signal OUT_SIG and the reference signal VREF_IN are not 180° out of phase, the operation which is executed by the differential amplifier 122 included in the receiving circuit 120 is a comparison operation to compare the external signal OUT_SIG with the reference signal VREF_IN. Therefore, the differential amplifier 122 is called as “psudo differential amplifier” in the present invention.
The differential amplifier 122 of the receiving circuit 120 to receive the external signal OUT_SIG includes first to third NMOS transistors N15 to N17 and first and second PMOS transistors P14 and P15. The first NMOS transistor N15 controls an amount of current flowing from a drain-connected driving node DVND2 to a source-connected common node COMN2 in response to the reference signal VREF_IN applied to a gate thereof. The second NMOS transistor N16 controls an amount of current flowing from a drain-connected output node OUND2 to the source-connected common node COMN2 in response to the external signal OUT_SIG applied to a gate thereof. The first and second PMOS transistors P14 and P15 are coupled to each other in a current mirror type among a power supply voltage terminal VDD, the driving node DVND2 and the output node OUND2 in order to control an amount of current in such a manner that the amount of current flowing into the driving node DVND2 is the same as that flowing into the output node OUND2. The third NMOS transistor N17 controls an amount of current flowing between the common node COMN2 and a ground voltage terminal VSS in response to the enable signal applied to a gate thereof.
The signal driving unit 124 of the receiving circuit 120 to receive the external signal OUT_SIG includes a third PMOS transistor P16 and a fourth NMOS transistor N18. The third PMOS transistor P16 controls an amount of current flowing from a source-connected power supply voltage terminal VDD to a drain-connected driving node KND2 in response to a comparison signal COMP_VOL from the output node OUND2 of the differential amplifier 122. The fourth NMOS transistor N18 controls an amount of current flowing from a drain-connected driving node KND2 to a source-connected ground voltage terminal VSS in response to the comparison signal COMP_VOL from the output node OUND2 of the differential amplifier 122.
Since the external signal OUT_SIG applied to the receiving circuit 120 is a signal which is not known in its own signal type, the original value of the external signal OUT_SIG cannot be predicted while the external signal OUT_SIG is distorted or deformed through the signal transmission. It is not easy to determine an internal signal IN_SIG based on the external signal OUT_SIG in which the distortion or deformity is caused via the signal transmission.
Accordingly, in the conventional signal receiving circuit, the reference signal VREF_IN having a constant voltage level is input into the receiving circuit 120 with the external signal OUT_SIG in order to determine a voltage level of the internal signal IN_SIG which is correspondent to the external signal OUT_SIG.
That is, even if the external signal OUT_SIG is distorted or deformed by an unexpected noise, the internal signal IN_SIG can be in compliance with the external signal OUT_SIG based on a relatively exact value, by estimating a logic level of the external signal OUT_SIG based on the reference signal VREF_IN and then generating the internal signal IN_SIG.
However, as mentioned above, to implement the receiving circuit 120 to receive the external signal OUT_SIG, the reference signal VREF_IN is additionally and inevitably used with the external signal OUT_SIG.
That is, since the reference signal VREF_IN has to be used with the external signal OUT_SIG, an additional dedicated pad for receiving the reference signal VREF_IN has to be provided together with a dedicated pad for receiving the external signal OUT_SIG.
At this time, although only one dedicated pad for receiving the reference signal VREF_IN is shown in FIG. 1, a member of dedicated pads can be required to comply with various functions of the semiconductor devices and this large number of dedicated pads increase the development cost with the tendency of high integration in semiconductor modules.
When the signal receiving circuit to receive a signal from an external circuit is applied to a synchronous memory such as a SDRAM (Synchronous Dynamic Random Access Memory), a synchronization unit 160 can be further included in the signal receiving circuit. The synchronization unit 160 synchronizes the internal clock signal iCLK, which is output as a result of the receiving circuit 100 to receive the positive clock signal CLK and the negative clock signal CLKb, with the internal signal IN_SIG, which is output as a result of the receiving circuit 120 to receive the external signal OUT_SIG.
In this case, if the maximum and minimum potential levels VILmax and VIHmin of the positive and negative clock signals CLK and CLKb is varied according to the external environment of the semiconductor device but the potential level of the reference voltage VREF_IN is not varied, the activation and inactivation sections of the internal clock signal ICLK which is produced by receiving the positive clock signal CLK and the negative clock signal CLKb are varied but the activation and inactivation sections of the internal signal IN_CLK which is produced by receiving the external signal OUT_SIG based on the reference voltage VREF_IN are not varied. Therefore, there is a problem in that the set up and hold time characteristics of the synchronized internal signal SYNC_IN_SIG are changed in the synchronization unit 160.
For example, when the maximum and minimum potential levels VILmax and VIHmin of the positive and negative clock signals CLK and CLKb are generally increased, the receiving circuit 100 to receive the positive and negative clock signals CLK and CLKb produces the internal clock signal iCLK at a high speed more than usual. However, since the potential level of the reference voltage VREDF_IN is not varied, the receiving circuit 120 to receive the external signal OUT_SIG produces the internal signal IN_SIG without a change of the operation speed. If the synchronization of the internal clock signal iCLK and the internal signal IN_SIG, which are changed with a different timing, is carried out in the synchronization unit 160, the synchronized internal signal SYNC_IN_SIG is output with a change of the set up and hold time characteristics.
On the contrary, if the maximum and minimum potential levels VILmax and VIHmin of the positive and negative clock signals CLK and CLKb is not varied but the potential level of the reference voltage VREF_IN is varied according to the external environment of the semiconductor device, the activation and inactivation sections of the internal clock signal iCLK which is produced by receiving the positive clock signal CLK and the negative clock signal CLKb are varied but the activation and inactivation sections of the internal signal IN_CLK which is produced by receiving the external signal OUT_SIG based on the reference voltage VREF_IN are varied. Therefore, there is a problem in that the set up and hold time characteristics of the synchronized internal signal SYNC_IN_SIG are changed in the synchronization unit 160.
When the signal receiving circuit is actually used in the semiconductor device, the variation of the reference voltage VREF_IN in the potential level or the variation of the positive and negative clock signals CLK and CLKb in the maximum and minimum potential levels VILmax and VIHmin can be caused due to the various environments, even though some cases are mentioned above. Therefore, the set up and hold time characteristics of the synchronized internal signal SYNC_IN_SIG can be frequently changed in the synchronization unit.
As mentioned above, when the set up and hold time characteristics of the synchronized internal signal SYNC_IN_SIG is changed, other circuits (not shown) in the semiconductor device which operate based on this set up and hold time characteristics undergo the fluctuation in the operation timing. As a result, the semiconductor device cannot execute a predetermined normal operation.